Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often referred to by the number of transistors, for example, six-transistor (6T) SRAM cell, eight-transistor (8T) SRAM cell, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of complementary bit-lines), which is used for writing a bit into, or reading a bit from, the SRAM cell.
Generally, electronic circuits have a significant data storage capacity. Such a capacity is reached with large memories formed of several memory blocks for physical or logical reasons. A memory controller enables the other functions of the electronic circuit to see all the memory blocks as a single memory, in terms of address.
Memory blocks may have a single-port architecture. In other words, as seen from the other electronic circuit functions, a single-port block can only perform one read operation or one write operation at the same time. This memory block architecture enables avoiding too complex memory architectures, or architectures consuming too much circuit surface area. However, it may sometimes be desirable for some functions of the electronic circuit to simultaneously perform a read operation and a write operation, with no address constraint.
A known approach to this problem is to use dual-port memories capable of performing two operations at the same time. The disadvantages of dual-port memories may be their low densities and high access times. Such memories may be poorly adapted to the storage of large data words.
Typically, an SRAM cell includes two pass-gate transistors, through which a bit can be read from or written into the SRAM cell. This type of SRAM cell is referred to as a single port SRAM cell. Another type of SRAM cell is referred to as dual port SRAM cell, which includes four pass-gate transistors.
With two ports, the bit stored in the SRAM cell can be read from port-A and port-B simultaneously. This allows for parallel operations by different applications. Moreover, if a first SRAM cell and a second SRAM cell are in a same column or a same row, a read operation to the first SRAM cell can also be performed simultaneously with a write operation on the second SRAM cell.
Basic SRAM architectures are based on various bit cells available, for example, a single port memory can be built with 6T cells and dual port memory can be built from 8T cells. There are 2 types of dual port 8T cells available, in one type one port can only do read and the other port can only do write at the same time and it may be referred to as 1R1W, while in the other type of 8T cell each port is capable of doing both read or write at the same time and it is referred to as 2R2W.
Often, a pure 2R2W is not needed, but two ports supporting write simultaneously and only one port for read and write simultaneously is needed instead. In such scenarios one approach is to use 2R2W memory as a 2W/1R2W but this approach uses 2R2W bit cells which may be difficult cells to design and control both at process level (stability) and design level (contention of address between two ports leading to performance penalty).
Pseudo dual port memories are possible using 6T cells that may perform two operations in one clock cycle, for example, using both the positive and negative edge of the clock to perform two operations or generating internal logic to enable two operations with the positive edge of the clock. However, the disadvantages of such an approach include the frequency being less than half, using both edges of clock is not preferred since both the edges are not aligned at the system-on-chip (SoC) level (e.g. clock jitters/skew), and also sequencing of operations is complex for internal logic.
There are other approaches in which multiple single port memories use a complex contention handling logic to realize multi port operations (e.g. U.S. Pat. No. 8,671,262 to the present Assignee). But, multiple cycles are used to handle contention and such approaches are not single cycle. The frequency can be on the order of a base single port memory, but the approaches need complex handling logic, and also do not provide single cycle operation, e.g. an operation is distributed across multiple clock cycles (i.e. latency is by default).